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1 1 1 1 1 white electronic designs corporation ? (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx september 2002 rev. 2 8mx72 synchronous dram + 16mb flash mixed module multi-chip package features package: 275 plastic ball grid array (pbga), 32mm x 25mm commercial, industrial and military temperature ranges weight: wedpnf8m722v-xbx - 2.5 grams typical sdram performance features organized as 8m x 72 high frequency = 100, 125mhz single 3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of system clock cycle internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst length 1,2,4,8 or full page 4096 refresh cycles flash performance features user configurable as 2mx8, 1m x16 or 512k x 32 access times of 100, 120, 150ns 3.3 volt for read and write operations 1,000,000 erase/program cycles advanced* sector architecture one 16kbyte, two 8kbytes, one 32kbyte, and fifteen 64kbytes in byte mode one 8k word, two 4k words, one 16k word, and fifteen 32k word sectors in word mode. any combination of sectors can be concurrently erased. also supports full chip erase boot code sector architecture (bottom) embedded erase and program algorithms erase suspend/resume supports reading data from or programing data to a sector not being erased benefits 44% space savings reduced part count reduced i/o count 25% i/o reduction suitable for hi-reliability applications sdram upgradeable to 16m x 72 density (contact factory for information) * this data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.
2 2 2 2 2 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx fig. 1 notes: notes: notes: notes: notes: 1. dnu = do not use t op v iew p in c onfiguration
3 3 3 3 3 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx fig. 2 sdram f unctional b lock d iagrams flash
4 4 4 4 4 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx signal name signal name signal name signal name signal name pin number pin number pin number pin number pin number v cc d15, e15, f8, f10, f15, g4, h4, j14, j15, j16, j17, k2, k3, k4, k5, l14, l15, l16, m5, m14, m15, n4, n5, n7, n8, n14, p4, p5, p6, p7, p11, p12, p13, p14, r4, t15, u15, v15 gnd d4, d16, e4, f4, f7, f9, f11, f12, f13, g14, g15, h15, j2, j3, j4, j5, k14, k15, k16, k17, l4, l5, m4, n6, n9, n10, n11, n12 , n13, n15, p8, p9, p10, p15, r15, t4, u4, v4 fd0 - 15 e8, c8, e9, c9, c10, d11, c11, d12, d8, b8, d9, d10, e10, e11, e12, e13 ryby1 h5 rst a7 byte1 d13 fd16 - 31 c12, c15, a15, b9, b11, b13, a10, a12, c13, b15, b14, b10, b12, a9, a11, a14 ryby2 a8 byte2 a13 fa1-19 f14, f5, e7, e6, e5, d6, d5, c6, c5, c4, b6, b5, b4, a6, a5, a4, c14, d7, c7 fcs1 h14 fcs2 e14 fwe b7 foe d14 a0 - a11 v12, u13, v13, v14, t14, r13, t13, r12, t12, r11, u12, t11 ba0 - 1 u11, v11 cs0 h3 we0 e3 clk0 c3 cke0 b3 ras0 g3 cas0 f3 dqml0 h2 dqmh0 d3 cs1 h18 we1 j18 clk1 b18 cke1 a18 ras1 g18 cas1 f18 dqml1 e18 dqmh1 c18 cs2 t18 we2 r18 clk2 l18 cke2 k18 ras2 u18 cas2 v18 dqml2 v17 dqmh2 m18 cs3 u3 we3 v3 clk3 m3 cke3 l3 ras3 t3 p ackage p inout l isting
5 5 5 5 5 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx signal name signal name signal name signal name signal name pin number pin number pin number pin number pin number p ackage p inout l isting ( continued ) cas3 r3 dqml3 u2 dqmh3 n3 cs4 t10 we4 u9 clk4 r9 cke4 r10 ras4 u10 cas4 v10 dqml4 v9 dqmh4 t9 dq0 - 15 e1, f1, e2, g1, f2, h1, j1, g2, a3, a2, b2, c2, b1, d2, c1, d1, dq16 - 31 e16, f16, g16, h16, e17, f17, g17, h17, d18, a17, b17, c17, d17, a16, b16, c16 dq32 - 47 r17, t17, u16, v16, t16, r16, u17, p18, n16, p16, p17, m16, m17, n17, n18, l17 dq48 - 63 r1, p2, t1, r2, p3, u1, v2, t2, m2, n2, l2, m1, p1, n1, l1, k1 dq64 - 79 u8, u6, v5, v6, u7, u5, v7, v8, r8, r6, t8, t6, r7, r5, t7, t5 dnu f6, g5, r14, u14, v1
6 6 6 6 6 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx dc e lectrical c haracteristics a nd o perating c onditions (n otes 1, 3) (vcc = +3.3v 0.3v; ta = -55c to +125c) parameter/condition parameter/condition parameter/condition parameter/condition parameter/condition symbol symbol symbol symbol symbol units units units units units min min min min min max max max max max supply voltage v cc 3 3.6 v input high voltage: logic 1; all inputs (4) v ih 0.7 x vcc v cc + 0.3 v input low voltage: logic 0; all inputs (4) v il -0.3 0.8 v sdram sdram sdram sdram sdram input leakage current: any input 0v - v in - v cc i i -5 5 a (all other pins not under test = 0v) sdram input leakage address current (all other pins not under test = 0v) i i -25 25 a sdram output leakage current: i/os are disabled; 0v - v out - v cc i oz -5 5 a sdram output high voltage (i out = -4ma) v oh 2.4 ? v sdram output low voltage (i out = 4ma) v ol ? 0.4 v flash flash flash flash flash flash input leakage current (v cc = 3.6, v in = gnd or v cc) i li 10 a flash output leakage current (v cc = 3.6, v in = gnd or v cc) i lox8 10 a flash output high voltage (i oh = -2.0 ma, v cc = 3.0) v oh1 0.85 x v cc v flash output low voltage (i ol = 5.8 ma, v cc = 3.0) v o l 0.45 v flash low v cc lock-out voltage (5) v lko 2.3 2.5 v notes: 1. all voltages referenced to vss. 2. this parameter is not tested but guaranteed by design. f = 1 mhz, ta = 25c. 3. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (vcc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the tref refresh requirement is exceeded. 4. vih overshoot: vih (max) = vcc + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. vil undershoot: vil (min) = -2v for a pulse width 3ns. 5. guaranteed by design, but not tested. a bsolute m aximum r atings p p p p p arameter arameter arameter arameter arameter unit unit unit unit unit supply voltage range (v cc ) -0.5 to +4.0 v signal voltage range -0.5 to vcc +0.5 v operating temperature t a (mil) -55 to +125 c operating temperature t a (ind) -40 to +85 c storage temperature, plastic -65 to +150 c flash endurance (write/erase cycles) 1,000,000 min. cycles note: note: note: note: note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. s dram c apacitance (n ote 2) p p p p p arameter arameter arameter arameter arameter symbol symbol symbol symbol symbol max max max max max unit unit unit unit unit input capacitance: clk c i1 8pf sdram addresses, ba 0-1 input capacitance c a 32 pf input capacitance: all other input-only pins c i2 8pf input/output capacitance: i/os c io 12 pf flash address capacitance f a 15 pf flash data capacitance f d 10 pf foe, fwe, rst 20 pf f lash d ata r etention parameter parameter parameter parameter parameter test conditions test conditions test conditions test conditions test conditions min min min min min unit unit unit unit unit minimum pattern data 150c 10 years retention time 125c 20 years
7 7 7 7 7 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx the 64mbyte (512mb) sdram is a high-speed cmos, dy- namic random-access ,memory using 5 chips containing 134, 217, 728 bits. each chip is internally configured as a quad-bank dram with a synchronous interface. each of the chip?s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. accesses begin with the registration of an active com- mand, which is then followed by a read or write com- mand. the address bits registered coincident with the ac- tive command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-11 select the row). the address bits registered coincident with the read or write command are used to select the starting column lo- cation for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 64mb sdram uses an internal pipelined architecture to achieve high-speed operation. this architecture is compat- ible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seam- less, high-speed, random-access operation. the 64mb sdram is designed to operate in 3.3v, low- power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl compatible. sdrams offer substantial advances in dram operating performance, in- cluding the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change col- umn addresses on each clock cycle during a burst access. icc s pecifications a nd c onditions (n otes 1,2,3,4) (vcc = +3.3v 0.3v; ta = -55c to +125c) parameter/condition parameter/condition parameter/condition parameter/condition parameter/condition symbol symbol symbol symbol symbol max max max max max units units units units units sdram operating current: active mode; i cc1 750 ma burst = 2; read or write; t rc = t rc (min); cas latency = 3 (5, 6, 7); fcs = high sdram standby current: active mode; cke = high; cs = high; fcs = high; i cc3 250 ma all banks active after t rcd met; no accesses in progress (5, 7, 8) sdram operating current: burst mode; continuous burst; fcs = high i cc4 750 ma read or write; all banks active; cas latency = 3 (5, 6, 7) sdram self refresh current; fcs = high (14) i cc7 10 ma flash v cc active current for read : fcs = v il , foe = v ih , f = 5mhz (9, 13); cs = high, cke = low i fcc1 45 ma flash v cc active current for program or erase: fcs = v il , foe = v ih (10, 13); cs = high, cke = low i fcc2 80 ma standby current: v cc = max, cs = high, cke = low, fcs = v ih (13) i fcc3 80 ma notes: 1. all voltages referenced to vss. 2. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (vcc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the tref refresh requirement is exceeded. 3. ac timing and icc tests have vil = 0v and vih = 3v, with timing referenced to 1.5v crossover point. 4. icc specifications are tested after the device is properly initialized. 5. icc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 6. the icc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 7. address transitions average one transition every two clocks. 8. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid vih or vil levels. 9. the icc current listed includes both the dc operating current and the frequency dependent component (at 5 mhz). the frequency component typically is less than 8 ma/mhz, with oe at vih. 10. icc active while embedded algorithm (program or erase) is in progress. 11. maximum icc specifications are tested with vcc = vcc max. 12. automatic sleep mode enables the low power mode when addressed remain stable for tacc + 30 ns. 13. sdram inactive and power down mode, all banks idle. 14. self refresh available in commercial and industrial temperatures only. sdram description
8 8 8 8 8 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx sdram functional description initialization burst length burst type register definition mode register read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. accesses begin with the registration of an active com- mand which is then followed by a read or write com- mand. the address bits registered coincident with the ac- tive command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-11 select the row). the address bits (a0-8) registered coincident with the read or write command are used to select the start- ing column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information cover- ing device initialization, register definition, command de- scriptions and device operation. sdrams must be powered up and initialized in a predefined manner. operational procedures other than those speci- fied may result in undefined operation. once power is ap- plied to vdd and vddq (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within tim- ing constraints specified for the clock pin), the sdram re- quires a 100s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop com- mands should be applied. once the 100s delay has been satisfied with at least one com- mand inhibit or nop command having been applied, a precharge command should be applied. all banks must be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. the mode register is used to define the specific mode of operation of the sdram. this definition includes the selec- tion of a burst length, a burst type, a cas latency, an oper- ating mode and a write burst mode, as shown in figure 3. the mode register is programmed via the load mode reg- ister command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 speci- fies the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initi- ating the subsequent operation. violating either of these requirements will result in unspecified operation. read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in fig- ure 3. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown opera- tion or incompatibility with future versions may result. when a read or write command is issued, a block of col- umns equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean- ing that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-8 when the burst length is set to two; by a2-8 when the burst length is set to four; and by a3-8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full- page bursts wrap within the page if the boundary is reached. accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column ad- dress, as shown in table 1.
9 9 9 9 9 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx t able 1 - b urst d efinition burst starting column order of ac cesses within a burst length address a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-9/8/7 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (y) (location 0-y) ?cn - 1, cn? type = sequent ial type = interleaved fig. 3 m ode r egister d efinition notes: notes: notes: notes: notes: 1. for full-page accesses: y = 512. 2. for a burst length of two, a1-8 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-8 select the block-of-four burst; a0-1 select the starting column within the block. 4. for a burst length of eight, a3-8 select the block-of-eight burst; a0-2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-8 select the unique column to be accessed, and mode register bit m3 is ignored.
10 10 10 10 10 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx cas l atency fig. 4 cas latency operating mode write burst mode table 2 - cas latency table 2 - cas latency table 2 - cas latency table 2 - cas latency table 2 - cas latency allowable operating allowable operating allowable operating allowable operating allowable operating frequency (mhz) frequency (mhz) frequency (mhz) frequency (mhz) frequency (mhz) cas cas cas cas cas cas cas cas cas cas speed speed speed speed speed latency = 2 latency = 2 latency = 2 latency = 2 latency = 2 latency = 3 latency = 3 latency = 3 latency = 3 latency = 3 -100 75 100 -125 100 125 commands the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n +m. the i/os will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the rel- evant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the i/os will start driving after t1 and the data will be valid by t2. table 2 indicates the operating fre- quencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may resuself self test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. the normal operating mode is selected by setting m7and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. the truth table provides a quick reference of available com- mands. this is followed by a written description of each command. three additional truth tables appear following the operation section; these tables provide current state/ next state information.
11 11 11 11 11 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx ba0, ba1 inputs selects the bank, and the address pro- vided on inputs a0-11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 se- lects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the i/os sub- ject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the correspond- ing i/os will be high-z two clocks later; if the dqm signal was registered low, the i/os will provide valid data. the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 selects the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively dese- lected. operations already in progress are not affected. the no operation (nop) command is used to perform a nop to an sdram which is selected (cs is low). this pre- vents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. the mode register is loaded via inputs a0-11. see mode register heading in the register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the table 3 truth table - commands and dqm operation (n ote 1) name (function) name (function) name (function) name (function) name (function) cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we dqm dqm dqm dqm dqm addr addr addr addr addr i/os i/os i/os i/os i/os command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) ( 3) l l h h x bank/row x read (select bank and column, and start read burst) (4) l h l h l/h 8 bank/col x write (select bank and column, and start write burst) (4) l h l l l/h 8 bank/col v alid burst terminate l h h l x x active precharge (deactivate row in bank or banks) ( 5) l l h l x code x auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x x x load mode register (2) l l l l x op-code x write enable/output enable (8) ? ? ? ? l ? active write inhibit/output high-z (8) ? ? ? ? h ? high-z notes: notes: notes: notes: notes: 1. cke is high for all commands shown except self refresh. 2. a0-11 define the op-code written to the mode register. 3. a0-11 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-8 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto pr echarge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the i/os during writes (zero-clock delay) and reads (two-clock delay). load mode register no operation (nop) command inhibit active read write
12 12 12 12 12 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx tered read or write command prior to the burst termi- nate command will be truncated. auto refresh is used during normal operation of the sdram and is analagous to cas-before-ras (cbr) re- fresh in conventional drams. this command is nonper- sistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh control- ler. this makes the address bits ?don?t care? during an auto refresh command. each 128mb sdram requires 4,096 auto refresh cycles every refresh period (tref). provid- ing a distributed auto refresh command will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be is- sued in a burst at the minimum cycle rate (trc), once every refresh period (tref). the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data with- out external clocking. the self refresh command is initi- ated like an auto refresh command except cke is dis- abled (low). once the self refresh command is regis- tered, all the inputs to the sdram become ?don?t care,? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to tras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defined as a signal cycling within timing constraints speci- fied for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands is- sued (a minimum of two clocks) for txsr, because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh com- mands must be issued as both self refresh and auto refresh utilize the row refresh counter. the starting column location. the value on input a10 deter- mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the i/os is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be writ- ten to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (trp) after the precharge command is is- sued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. other- wise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being is- sued to that bank. auto precharge is a feature which performs the same in- dividual-bank precharge function described above, with- out requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/ row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonper- sistent in that it is either enabled or disabled for each indi- vidual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (trp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time. the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently regis- precharge auto precharge auto refresh self refresh* burst terminate * self refresh available in commercial and industrial temperatures only.
13 13 13 13 13 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx parameter parameter parameter parameter parameter symbol symbol symbol symbol symbol -100 -100 -100 -100 -100 -125 -125 -125 -125 -125 unit unit unit unit unit min min min min min max max max max max min min min min min max max max max max access time from clk (pos. edge) cl = 3 t ac 76ns cl = 2 t ac 76ns address hold time t ah 11 ns address setup time t as 22 ns clk high-level width t ch 33 ns clk low-level width t cl 33 ns clock cycle time (6) cl = 3 t ck 10 8 ns cl = 2 t ck 13 10 ns cke hold time t ckh 11 ns cke setup time t cks 22 ns cs, ras, cas, we, dqm hold time t cmh 11 ns cs, ras, cas, we, dqm setup time t cms 22 ns data-in hold time t dh 11 ns data-in setup time t ds 22 ns data-out high-impedance time cl = 3 (7) t hz 76ns cl = 2 (7) t hz 76ns data-out low-impedance time t lz 11 ns data-out hold time (load) t oh 33 ns data-out hold time (no load) (8) t oh n 1.8 1.8 ns active to precharge command t ras 50 120,000 45 120,000 ns active to active command period t rc 70 68 ns active to read or write delay t rcd 20 20 ns refresh period (4,096 rows) ? commercial, industrial t ref 64 64 ms refresh period (4,096 rows) ? military t ref 16 16 ms auto refresh period t rfc 70 70 ns precharge command period t rp 20 20 ns active bank a to active bank b command t rrd 15 16 ns transition time (9) t t 0.3 1.2 0.3 1.2 ns write recovery time (10) t wr 1 clk + 7ns 1 clk + 7ns ? (11) 15 15 ns exit self refresh to active command t xsr 80 78 ns sdram e lectrical c haracteristics a nd r ecommended ac o perating c haracteristics (n otes 1, 2, 3, 4, 5) notes: notes: notes: notes: notes: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (vcc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the tref refresh requirement is exceeded. 3. in addition to meeting the transition rate specification, the clock and cke must transit between vih and vil (or between vil and vih) in a monotonic manner. 4. outputs measured at 1.5v with equivalent load: 5. ac timing and icc tests have vil = 0v and vih = 3v, with timing referenced to 1.5v crossover point. 6. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including twr, and precharge commands). cke may be used to reduce the data rate. 7. thz defines the time at which the output achieves the open circuit condition; it is not a reference to voh or vol. the last valid data element will meet toh before going high-z. 8. guaranteed by design, but not tested. 9. ac characteristics assume tt = 1ns. 10. auto precharge mode only. the precharge timing budget (trp) begins 7.5ns/ 7ns after the first clock delay, after the last write is executed. 11. precharge mode only.
14 14 14 14 14 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx the 16mbit (2mb) 3.3 volt-only flash memory is organized as 2,097,152 words of 8 bits each,1,048,576 words of 16 bits each or 524,288 words of 322 bit each. bytes. the byte-wide (x8) data appears on fd 0-7 ; the word-wide (x16) data appears on fd 0-15 , double-word-wide (x32) data ap- pears on fd 0-32 . this device requires only a single 3.3 volt vcc supply to perform read, program, and erase opera- tions. a standard eprom programmer can also be used to program and erase the device. this device features unlock bypass programming and in- system sector protection/unprotection. this device offers access times of 100, 120 and 150ns, al- lowing operation without wait states. to eliminate bus con- tention the device has separate chip selects (fcs 1-2 ), write enable (fwe) and output enable (foe) controls. the device requires only a single 3.3 volt power supply for both read and write functions. internally generated and regulated volt- ages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard micropro- cessor write timings. register contents serve as input to an internal state-machine that controls the erase and program circuitry. write cycles also internally latch addresses and data needed for the programming circuitry. write cycles also in- ternally latch addresses abd data needed for the program- notes: notes: notes: notes: notes: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (vcc must be powered up simultaneously.) the two auto refresh command wake- ups should be repeated any time the tref refresh requirement is exceeded. 3. ac characteristics assume tt = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between vih and vil (or between vil and vih) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: 6. ac timing and icc tests have vil = 0v and vih = 3v, with timing referenced to 1.5v crossover point. 7. timing actually specified by tcks; clock(s) specified as a reference only at minimum cycle rate. 8. timing actually specified by twr plus trp; clock(s) specified as a reference only at minimum cycle rate. 9. timing actually specified by twr. 10. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 11. jedec and pc100 specify three clocks. sdram ac f unctional c haracteristics (n otes 1,2,3,4,5,6) parameter/condition parameter/condition parameter/condition parameter/condition parameter/condition symbol symbol symbol symbol symbol -100 -100 -100 -100 -100 -125 -125 -125 -125 -125 units units units units units read/write command to read/write command (10) t ccd 11t ck cke to clock disable or power-down entry mode (7) t cked 11t ck cke to clock enable or power-down exit setup mode (7) t ped 11t ck dqm to input data delay (10) t dqd 00t ck dqm to data mask during writes t dqm 00t ck dqm to data high-impedance during reads t dqz 22t ck write command to input data delay (10) t dwd 00t ck data-in to active command (8) t dal 45t ck data-in to precharge command (9) t dpl 22t ck last data-in to burst stop command (10) t bdl 11t ck last data-in to new read/write command (10) t cdl 11t ck last data-in to precharge command (9) t rdl 22t ck load mode register command to active or refresh command (11) t mrd 22t ck data-out to high-impedance from precharge command (10) cl = 3 t roh 33t ck cl = 2 t roh 2?t ck flash description
15 15 15 15 15 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the in- ternal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 4 lists the device bus operations, the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. ming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program com- mand sequence. this initiates the embedded program al- gorithm ? an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. the unlock bypass mode faciclitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm ? an internal algorithm that automaticaally preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether as program or erase operation is complete by observing the ry/by1-2 pin, or by reading fd 7 /fd 23 (data polling) and fd 6 /fd 22 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another com- mand. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectords. the device is fully erased when shipped from the factory. hardware data protection measures include a low vcc de- tector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables bith program and erase operations in any combi- nation of sectors of memory. this can be achieved in-sys- tem or via programming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or pro- gram data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset (rst) pin terminates any operation in progress and resets the internal state machine to reading array data. the rst pin may be tied to the reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from flash memory. the device offers two power saving features. when ad- dresses have been stable for specified amount of time, the device enters the automatic sleep mode. the system can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes word/byte configuration the byte1 pin controls whether the device data i/o pins fd o-15 operate in the byte or word configuration. if the byte1 pin is set at logic ?1?, the device is in word configuration, fd 0-15 are active and controlled by fcs 1 and foe. if the byte1 pin is set at logic ?0?, the device is in byte con- figuration, and only data i/o pins fd 0-7 are active and con- trolled by fcs 1 and foe. the data i/o pins fd 8-14 are tri stated, and the fd 15 pin is used as an input for the lsb (fa-1) ad- dress function. the byte2 pin controls whether the device data i/o pins fd 16-31 operate in the byte or word configuration. if the byte2 pin is set at logic ?1?, the device is in word configu- ration, fd0-15 are active and controlled by fcs 2 and foe. if the byte2 pin is set at logic ?0?, the device is in byte con- figuration, and only data i/o pins fd 0-7 are active and con- trolled by fcs 2 and foe. the data i/o pins fd 8-14 are tri stated, and the fd 15 pin is used as an input for the lsb (fa-1) ad- dress function. to read array data from the outputs, the system must drive the fcs 1-2 and foe pins to vil. fcs 1-2 are the power con- trols and select the devices. foe is the output control and gates array data to the output pins. fwe should remain at vih. the byte1-2 pins determine whether the device out- puts array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures requirements for reading array data
16 16 16 16 16 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx t able 4 - device bus operations legend: legend: legend: legend: legend: l = logic low = v il x = don?t care fd out = flash data out h = logic high = v ih fa in = flash address in v id = 12.0 0.5v fd in = flash data in notes: notes: notes: notes: notes: 1. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the "sector protect ion/unprotection" section. 2. addresses are fa18: fa0 in word mode (byte1-2 = v ih ), fa18: fa-1 in byte mode (byte1-2 = v il ) to writes a command or command sequence (which in- cludes programming data to the device and erasing sec- tors of memory), the system must drive fwe and fcs 1-2 to vil, and foe to vih. for program operations, the byte1-2 pins determine whether the device accepts program data in bytes or words. refer to ?word/ byte configuration? for more information. the device features an unlock bypass mode to facilitate write commands/command sequences that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device data outputs. the device remains en-abled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the flash ac read-only operations table for timing specifica- tions and to figure 11 for the timing diagram. ifcc1 in the icc specifications and conditions table represents the ac- tive current specification for reading array data. faster programming. once the device enters the unlock by- pass mode, only two write cycles are required to program a byte, instead of four. an erase operation can erase one sector, multiple sectors, or the entire device. table 5 indicates the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?flash command defini-tions? section has details on eras- ing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on fd 7-0 and fd 23-16 re- spectively . stan-dard read cycle timings apply in this mode. refer to the ?autoselect mode? and ?autoselect command sequence? sections for more information. ifcc2 in the dc characteristics table represents the active current specifications for the write mode. the ?flash ac characteristics? section contains timing specification tables and timing diagrams for write operations. fd fd fd fd fd 8-15 8-15 8-15 8-15 8-15 /fd /fd /fd /fd /fd 24-31 24-31 24-31 24-31 24-31 operation operation operation operation operation fc fc fc fc fc s s s s s 1-2 1-2 1-2 1-2 1-2 foe foe foe foe foe fwe fwe fwe fwe fwe rst rst rst rst rst addresses (2) addresses (2) addresses (2) addresses (2) addresses (2) fd fd fd fd fd 0-7 0-7 0-7 0-7 0-7 /fd1 /fd1 /fd1 /fd1 /fd1 6-23 6-23 6-23 6-23 6-23 byte1-2 byte1-2 byte1-2 byte1-2 byte1-2 byte1-2 byte1-2 byte1-2 byte1-2 byte1-2 =vih =vih =vih =vih =vih =vil =vil =vil =vil =vil read l l h h fain fdout fdout fd8-14, 24-30 = high z write l h l h fain fdout fdout fd15, 31 = fa-1 standby vcc 0.3v x x vcc 0.3v x high z high z high z output disable l h h h x high z high z high z reset x x x l x high z high z high z sector address sector protect (1) l h l vid fa6 = l, fa1 = h, fdin x x fa0 = l sector address sector unprotect (1) l h l vid fa6 = l, fa1 = h, fdin x x fa0 = l temporary sector unprotect x x x vid ain fdin fdin high z
17 17 17 17 17 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx t t t t t able able able able able 5 - b 5 - b 5 - b 5 - b 5 - b ot ot ot ot ot tom tom tom tom tom b b b b b oot oot oot oot oot b b b b b l l l l l ock ock ock ock ock s s s s s ector ector ector ector ector a a a a a ddres ddres ddres ddres ddres s s s s s t t t t t able able able able able sector size sector size sector size sector size sector size (x8) address range (x8) address range (x8) address range (x8) address range (x8) address range sector sector sector sector sector a a a a a 18 18 18 18 18 a a a a a 17 17 17 17 17 a a a a a 16 16 16 16 16 a a a a a 15 15 15 15 15 a a a a a 14 14 14 14 14 a a a a a 13 13 13 13 13 a a a a a 12 12 12 12 12 (kbytes) (kbytes) (kbytes) (kbytes) (kbytes) (in hexidecimal) (in hexidecimal) (in hexidecimal) (in hexidecimal) (in hexidecimal) sa 0 0 0 0 0 0 0 x 16 00000h-03fffh sa 1 0 0 0 0 0 1 0 8 04000h-05fffh sa 2 0 0 0 0 0 1 1 8 06000h-07fffh sa 3 0 0 0 0 1 x x 32 08000h-0ffffh sa 4 0 0 0 1 x x x 64 10000h-1ffffh sa 5 0 0 1 0 x x x 64 20000h-2ffffh sa 6 0 0 1 1 x x x 64 30000h-3ffffh sa 7 0 1 0 0 x x x 64 40000h-4ffffh sa 8 0 1 0 1 x x x 64 50000h-5ffffh sa 9 0 1 1 0 x x x 64 60000h-6ffffh sa 10 0 1 1 1 x x x 64 70000h-7ffffh sa 11 1 0 0 0 x x x 64 80000h-8ffffh sa 12 1 0 0 1 x x x 64 90000h-9ffffh sa 13 1 0 1 0 x x x 64 a0000h-affffh sa 14 1 0 1 1 x x x 64 b0000h-bffffh sa 15 1 1 0 0 x x x 64 c0000h-cffffh sa 16 1 1 0 1 x x x 64 d0000h-dffffh sa 17 1 1 1 0 x x x 64 e0000h-effffh sa 18 1 1 1 1 x x x 64 f0000h-fffffh during an erase or program operation, the system may check the status of the operation by reading the status bits on fd7-0 and fd23-16 respectively. standard read cycle tim- ings and ifcc read specifications apply. refer to ?write op- eration status? for more information, and to ?flash ac char- acteristics? for timing diagrams. program and erase operation status when the system is not reading or writing to the device, it can place the device in standby mode. in this mode, cur- rent consump-tion is greatly reduced, and the outputs are placed in the high impedance state, independent of the foe input. the device enters the cmos standby mode when the fcs1- 2 and rst pins are held at vcc 0.3v. (note that this is a more restricted voltage range than vih.) if fcs 1-2 and rst are held at vih, but not within vcc 0.3v the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (tce ) for read access when the device is in either of these standby standby mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the au- tomatic sleep mode is independent of the fcs1-2, fwe, and foe control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. if cc5 in the dc characteristics table represents the automatic sleep mode current specification. automatic sleep mode the rst pin provides a hardware method of resetting the device to reading array data. when the rst pin is driven low for at least a period of trp or greater the device imme- diately terminates any operation in progress, tristates all out- put pins, and ignores all read/write commands for the dura- tion of the rst pulse. the device also resets the internal state machine to reading array data. the operation that was inter- rupted should be reinitiated once the device is ready to ac- cept another command sequence, to ensure data integrity. current is reduced for the duration of the rst pulse. when rst is held at vss 0.3v, the device draws cmos standby current (ifcc4). if rst is held at vil but not within vss rst: hardware reset pin
18 18 18 18 18 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx the autoselect mode provides sector protection verifica- tion, through identifier codes input codes output on fd7- 0. this mode is prima-rily intended for programming equip- ment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode re-quires vid (11.5v to 12.5v) on address pin fa9. ad- dress pins fa6, fa1, and fa0 must be as shown in table 6. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order ad- dress bits (see table 5). table 6 shows the remaining ad- dress bits that are ?don?t care.? when all necessary bits have been set as required, the programming equip-ment may then read the corresponding identifier code on fd7-0 or fd23-16 . to access the autoselect codes in-system, the host system can issue the autoselect command via the command regis- ter, as shown in table 7. this method does not require vid. see ?com-mand definitions? for details on using the autoselect mode. autoselect mode temporary sector unprotect this feature allows temporary unprotection of previously protected sector groups to change data-in system. the sector unprotect mode is activated by setting the rst pin to vid. during this mode, formerly protected sector can be programmed or erased by selecting the sector ad- dresses. once vid is removed from the rst pin, all the pre- viously protected sector groups will be protected again. figure 16 shows the algorithm and the timing diagram is shown in figure 17, for this feature. 0.3v, the standby current will be greater. the rst pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, en- abling the system to read the boot-up firmware from the flash memory. if rst is asserted during a program or erase operation, ry/ by1 pin remains ?0? (busy) until the internal reset operation is complete, which requires a time of tready (during embed- ded algorithms). the system can thus monitor ry/by1-2 to determine whether the reset operation is complete. if rst is asserted when a program or erase operation is not execut- ing (ry/by1-2 pins are ?1?), the reset operation is completed within a time of tready (not during embedded algorithms). the system can read data trh after the rst pin returns to vih. refer to the flash dc characteristics and hardware reset tables for rst parameters and to figure 19 for the timing diagram. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 7 for command definitions). in addition, the following hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level sig- nals during vcc power-up and power-down transitions, or from system noise. t able 6 - a utoselect c odes (h igh v oltage m ethod ) description description description description description fcs1-2 fcs1-2 fcs1-2 fcs1-2 fcs1-2 foe foe foe foe foe fwe fwe fwe fwe fwe fa fa fa fa fa 18 18 18 18 18 - - - - - 12 12 12 12 12 fa fa fa fa fa 11 11 11 11 11 - - - - - 10 10 10 10 10 fa fa fa fa fa 9 9 9 9 9 fa fa fa fa fa 8 8 8 8 8 - - - - - 7 7 7 7 7 fa fa fa fa fa 6 6 6 6 6 fa fa fa fa fa 5 5 5 5 5 - - - - - 2 2 2 2 2 fa fa fa fa fa 1 1 1 1 1 fa fa fa fa fa 0 0 0 0 0 fd fd fd fd fd 7 7 7 7 7 - - - - - 0 0 0 0 0 fd fd fd fd fd 23-16 23-16 23-16 23-16 23-16 sector protection llhsa xv id xlxh l verificaton 01h (protected) 00h (unprotected) 01h (protected) 00h (unprotected) l = logic low = vil, h = logic high = vih, sa = sector address, x = don't care l ow v cc w rite i nhibit when vcc is less than vlko, the device does not accept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than vlko. the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than vlko.
19 19 19 19 19 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx s ector p rotect /u nprotect a lgorithms s ector p rotect a lgorithm s ector u nprotect a lgorithm fig. 5
20 20 20 20 20 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx flash command definitions read array data upon initial device power-up the device defaults to read array data. no commands are required to retrieve data. the device is also ready to read array data after it has completed an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspend sectors, the device outputs status data. after completing a program- ming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more infor- mation on this mode. the system must issue the reset command to re-enable the device for reading array data if fd5 goes high, or while in the autoselect mode. see the ?reset command? section, next. see also ?requirements for reading array data? on the ?bus operations? section for more information. the data sheet read operations table provides the read parameters, and the read operations timing diagram shows the timing diagram. writing specific address and data commands or sequences into the command register initiates device operations. table 7 defines the valid register command sequences. w w w w w riting riting riting riting riting incor incor incor incor incor rect address and data values or writing them in rect address and data values or writing them in rect address and data values or writing them in rect address and data values or writing them in rect address and data values or writing them in improper sequence will reset the device to the read improper sequence will reset the device to the read improper sequence will reset the device to the read improper sequence will reset the device to the read improper sequence will reset the device to the read ar ar ar ar ar ray data ray data ray data ray data ray data. all addresses are latched on falling edge of fwe or fcs1-2, whichever occurs later. all data is latched on the rising edge of fwe or fcs1-2, whichever occurs first. refer to the ap- propriate timing diagrams in the ?flash ac characteristics? section. reset command writing the reset command to the device resets the device to reading array data. address bits are ?don't care? for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing be- gins. this resets the device to reading array data. once era- sure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before program- ming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect dur- ing erase suspend mode). if fd5 or fd21, respectively goes high during a program or erase operation, writing the reset command returns the de- vice to reading array data (also applies during erase suspend). w rite p ulse "g litch " p rotection noise pulses of less than 5ns (typical) on foe, fcs1-2 or fwe do not initiate a write cycle. l ogical i nhibit write cycles are inhibited by holding any one of foe = vil, fcs1-2 = vih or fwe = vih. to initiate a write cycle, fcs1-2 and fwe must be a logical zero while foe is a logical one. p ower -u p w rite i nhibit if fwe = fcs1-2 = vil and foe = vih during power up, the device does not accept commands on the rising edge of fwe. the internal state machine is automatically reset to reading array data on power-up. sector protection/ unprotection the hardware sector protection feature disables both pro- gram and erase operations in any sector. the hardware sec- tor unprotection feature re-enables both program and erase operations in previ-ously protected sectors. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. this operation requires vid on the rst pin only, and can be implemented either in-system or via programming equip- ment. the timing diagram is shown in figure 18. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unpro-tected sectors must first be protected prior to the first sector unprotect write cycle.
21 21 21 21 21 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx u nlock b ypass c ommand s equence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass com- mand sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle con- tains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard pro- gram command sequence, resulting in fast total program- ming time. table 7 shows the requirements for the com- mand sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are ?don't care? for both cycles. the device then returns to reading array data. figure 6 illustrates the algorithm for the program operation. see the erase/program operations table in the ?flash ac characteristics? for parameters, and to figure 12 for timing diagrams. a utoselect c ommand s equence the autoselect command sequence allows the host sys- tem to determine whether or not a sector is protected. table 7 shows the address and data requirements. this method is an alternative to that shown in table 6, which is intended for prom programmers and requires v id on address bit fa9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the sys- tem may read at any address any number of times, without initiating another command sequence. a read cycle containing a sector address (sa) and the ad- dress 02h in word mode (or 04h in byte mode) returns 02h in that sector is protected, or 00h if it is unprotected. refer to table 5 for valid sector addresses. the system must write the reset command to exit autoselect mode and return to reading array data.
22 22 22 22 22 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx p rogram o pera tion note: note: note: note: note: see table 7 for program command sequence. fig. 6 w ord /b yte p rogram c ommand s equence the system may program the devices by word or byte, de- pending on the state of the byte1-2 pins. programming is a four-bus-cycle operation. the program command se- quence is initiated by writing two unlock write cycles, fol- lowed by the program set-up command. the program ad- dress and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timing. the device automati- cally provides internally generated program pulses and veri- fies the programmed cell margin. table 7 shows the ad- dress and data requirements for the byte program com- mand sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using fd7, fd6, or ry/by1and fd23, 22 or ry/by2 respectively. see ?write operation sta- tus? for information on these status bits. any commands written to the device during the embed- ded program algorithm are ignored. note that a hardware hardware hardware hardware hardware reset reset reset reset reset immediately terminates the programming operation. the program command sequences should be reinitiated once the device has reset to reading array data, to ensure date integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? a bit cannot be programmed from a ?0? a bit cannot be programmed from a ?0? a bit cannot be programmed from a ?0? a bit cannot be programmed from a ?0? back to a ?1?. back to a ?1?. back to a ?1?. back to a ?1?. back to a ?1?. attempting to do so may halt the operation and set fd5 and fd21 respectively to ?1?, or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?.
23 23 23 23 23 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx e rase o pera tion 1. see table 5 for erase command sequence. 2. see "fd3 : sector erase timer" for more information. fig. 7 sector erase command sequence sector erase is six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a setup command. two additional un- lock write cycles are then followed by the address of the sector to be erased, and the sector erase command, which in turn invokes the embedded erase algorithm. table 7 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm au- tomatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time- chip erase is six bus cycle operation. the chip erase com- mand sequence is initiated by writing two unlock cycles, followed by a setup command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 7 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset hardware reset hardware reset hardware reset hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be re-initiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using fd7, fd6, or fd2, or ry/by1 and fd23, fd22, fd18 or ry/by2, respectively. see ?write operation status? for in- formation on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 6 illustrates the algorithm for the erase operation. see the erase/program operations tables in ?flash ac character- istics? for parameters, and to figure 12 for timings diagram. chip erase command sequence
24 24 24 24 24 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx the erase suspend command allows the system to inter- rupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50s time-out period during the sector erase command sequence. the erase suspend command is ig- nored if written during the chip erase operation or embed- ded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. ad- out of 50s begins. during the time-out period, additional sector addresses and sector erase commands may be writ- ten. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can out period resets the device to reading ar out period resets the device to reading ar out period resets the device to reading ar out period resets the device to reading ar out period resets the device to reading ar ray data ray data ray data ray data ray data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor fd3 and fd19, respectively to de- termine if the sector erase timer has timed out. see the ?fd3/fd19: sector erase timer? section. the time-out be- gins from the rising edge of the final fwe pulse in com- mand sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation. the sector erase com- mand sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using fd7, fd6, or fd2, or ry/by1 and fd23, fd22, or fd18, or ry/by2. see ?write operation status? for information on these status bits. figure 6 illustrates the algorithm for the erase operation. see the erase/program operations tables in the ?flash ac charac- teristics? for parameters, and to figure 12 for timings diagram. erase suspend/erase resume command sequence dresses are ?don't cares? when writing the erase suspend command. when the erase suspend command is written during a sec- tor erase operation, the device requires a maximum of 20s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sec- tors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on fd7-0 and fd23-16 respectively. the system can use fd7, or fd6, and fd2 and fd23 or fd22 and fd18 together re- spectively, to determine if a sector is actively erasing or is erase suspended. see "write operation status" for infor- mation on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-sus- pended sectors. the system can determine the status of the program operation using the fd7 or fd6 status bits and fd23 or fd22 status bits respectively, just as in the standard program operation. see the ?write operation status? for more information. the system may also write the autoselect command se- quence when the device is in the erase suspend mode. the device allows reading autoselect codes even at ad- dresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. the system must write the erase resume command (address bits are ?don't care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend com- mand can be written after the device has resumed erasing.
25 25 25 25 25 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the fwe or fcs1-2 pulses, wh ichever occurs first. pd = data to be programmed at location pa. data is latched on the rising edge of fwe or fcs1-2 pulses, whichever occurs first. sa = address of the sector to be erased. the combination of fa18-12 will uniquely select any sector. notes: 1. bus operations are defined in table 3. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits fa18-11 = don?t care for unlock and command cycles, unless pa or sa is required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if fd5 and fd21, res pectively goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the e rase suspend command is valid only during a sector erase operation. 12. the erase resume command is valid only during the erase suspend mode. 13. data bits fd8-15 and fd24-31, respectively are don?t cares for unlock and command cycles. 14. the command definitions refer to each flash device individually. t able 7 - c ommand d efinitions (14) bus cycles (notes 2, 3, 4, 13) bus cycles (notes 2, 3, 4, 13) bus cycles (notes 2, 3, 4, 13) bus cycles (notes 2, 3, 4, 13) bus cycles (notes 2, 3, 4, 13) first bus first bus first bus first bus first bus second bus second bus second bus second bus second bus third bus third bus third bus third bus third bus fourth bus fourth bus fourth bus fourth bus fourth bus fifth bus fifth bus fifth bus fifth bus fifth bus sixth bus sixth bus sixth bus sixth bus sixth bus cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle addr addr addr addr addr data data data data data addr addr addr addr addr data data data data data addr addr addr addr addr data data data data data addr addr addr addr addr data data data data data addr addr addr addr addr data data data data data addr addr addr addr addr data data data data data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 byte 4 aaa aa 555 55 aaa 90 x02 5b word 555 2aa 555 x01 225b byte 4 aaa aa 555 55 aaa 90 (sa) xx00 x04 01 word 555 2aa 555 (sa) xx00 x02 xx01 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 word 555 2aa 555 unlock bypass program (note 9) 2 xxx a0 pa pd unlock bypass reset (note10) 2 xxx 90 pa 00 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa 555 sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 word 555 2aa 555 555 2aa erase suspended (note 11) 1 xxx b0 erase resume (note 12) 1 xxx 30 bus bus bus bus bus write write write write write cycles cycles cycles cycles cycles req'd req'd req'd req'd req'd command command command command command sequence sequence sequence sequence sequence (note 1) (note 1) (note 1) (note 1) (note 1) device id, bottom boot block sector protect verify (note 7,8) autoselect
26 26 26 26 26 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx d ata p olling a lgorithm 1. fd7/fd23 should be rechecked even if fd5/fd21 = 1 because fd7/ fd23 may change simultaneously with fd5/fd21 respectively. va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any non-protected sector group address during chip erase fig. 8 write operation status the device provides several bits to determine the status of a write operation: fd2, fd3, fd5, fd6, and fd7 and fd18, fd19, fd21, fd22 and fd23 respectively. table 8 and the following subsections describe the functions of these bits. fd7, ry/by1, and fd6 and fd23, ry/by2, fd22 respectively each offer a method for determining whether a program or erase operation is complete or in progress. these bits are discussed first. fd7/fd23: data polling the data polling bit, fd7, indicates to the host system whether an embedded algorithm is in progress or com- pleted, or whether the device is in erase suspend data polling valid after the rising edge of the final fwe pulse in the program or erase command sequence. during the embedded program algorithm, the device out- puts on fd7/fd23 the complement of the datum pro- grammed to fd7/fd23. this fd7/fd23 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the da- tum programmed to fd7/fd23. the system must provide the program address to read valid status information on fd7/fd23. if a program address falls within a protected sec- tor, data polling on fd/fd237 is active for approximately 1s, then the device returns to reading array data. during the embedded erase algorithm, data polling pro- duces a ?0? on fd7/fd23. when the embedded erase al- gorithm is complete, or if the device enters the erase sus- pend mode, data polling produces a ?1? on fd7/fd23. this analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the de- vice outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on fd7/fd23. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on fd7/fd23 is active for approximately 100s, then the device returns to reading array data. if not all selected sectors are pro- tected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. when the system detects fd7 has changed from the complement to true data, it can read valid data at fd7-0
27 27 27 27 27 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx ?toggle bit i? on fd6/22 indicates whether an embedded program or erase algorithm is in progress or has been com- pleted, or whether the device has entered the erase sus- pend mode. toggle bit i may read at any address, and is valid after the rising edge of the final fwe pulse in the com- mand sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm opera- tion, successive read cycles to any address will result in fd6 toggling. (the system may use either foe or fcs1-2 to control the read cycles.) when operation is complete, fd6/ 22 stop toggling. after the erase command sequence is written, if all sectors selected for erasing are protected, fd6/22 toggles for ap- proximately 100s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use fd6/22 and fd2/fd18 respectively, to- gether to determine whether a sector is actively erasing or and fd23-16 respectively on the following read cycles. this because fd7 may change asynchronously with fd0-6 and fd16-22 respectively while flash output enable (foe) is asserted low. figure 14, data polling timings (during embed- ded algorithms), in the ?flash ac characteristics? section illustrates this. table 8 shows the outputs for data polling on fd7/fd23. figure 8 shows the data polling algorithm. ry/by1-2: ready/busy the ry/by1-2 is a dedicated, open drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by1-2 status is valid after the rising edge of the final fwe pulse in the command sequence. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase sus- pend mode.) if the output is high (ready), the device is ready to read array data (including during the erase sus- pend mode.), or is in the standby mode. table 8 shows the outputs for ry/by1-2. figures 11, 12, 13, 19 show ry/by1-2 for read, program, erase and reset op- erations, respectively. fd6/22: toggle bit i is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress) fd6/22 toggles. when the device enters the erase suspend mode, fd6 stops toggling. however, the system must also use fd2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use fd7 (see the subsection on ?fd7: data polling?). if a program address falls within a protected sector, fd6 also toggles for approximately 1s after the program com- mand sequence is written, then returns to reading array data. fd6 also toggles during erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 8 shows the outputs for ?toggle bit i? on fd6. figure 9 shows the toggle bit algorithm. figure 21 shows the toggle bit timing diagrams. figure 20 shows the difference between fd2 and fd6 in graphical form. see also the subsection on ?fd2: toggle bit ii?. fd2: toggle bit ii the ?toggle bit ii? on fd2, when used with fd6, indicates whether a particular sector is actively erasing (that is, the em- bedded erase algorithm is in progress) or whether that sec- tor is erase-suspended. ?toggle bit ii? is valid after the rising edge of the final fwe pulse in the command sequence. fd2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either foe or fcs to control the read cycles.) fd2 cannot distinguish whether the sector is ac- tively erasing or is erase-suspended. fd6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 8 to compare out- puts for fd2 and fd6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?fd2: toggle bit ii? explains the algorithm. see also the subsection on ?fd6: toggle bit i?. figure 21 shows the toggle bit timing diagrams. figure 20 shows the difference between fd2 and fd6 in graphical form.
28 28 28 28 28 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx t oggle b it a lgorithm 1. read toggle bit twice to detemine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as fd5 changes to 1. see text. fig. 9 reading toggle bits fd6/fd2 refer to figure 9 for the following discussion. whenever the system initially begins reading toggle bit status, it must read fd7-fd0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on fd7-0 on the following read cycle. however, if after the initial two read cycles, the system de- termines that the toggle bit is still toggling, the system also should note whether the value of fd5 is high (see the sec- tion on fd5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as the device has successfully completed the program or erase operation. if it is still tog- gling, the device did not complete the operation success- fully, and the system must write the reset command to re- turn to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and fd5 has not gone high. the system may continue to monitor the toggle bit and fd5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to per- form other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 9). fd5: exceeded timing limits fd5 will indicate whether the program or erase time has ex- ceeded the specified limits (internal pulse count). under these conditions fd5 will produce a ?1?. this is a failure condition that indicates the program or erase cycle was not successfully completed. the fd5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded timing limits, the fd5 bit will produce a ?1?. under both these conditions, the system must issue the reset command to return the device to reading array data.
29 29 29 29 29 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx notes: 1. fd5 switches to "1" when an embedded program or embedded erase operation has exceeded the maximum timing limits. see "fd5: e xceed timing limits" for more information. 2. fd7 and fd2 require valid address when reading status information. refer to the appropriate subsection for further details. t able 8 - w rite o pera tion s tatus status status status status status fd fd fd fd fd 7 7 7 7 7 (2) (2) (2) (2) (2) fd fd fd fd fd 6 6 6 6 6 fd fd fd fd fd 5 5 5 5 5 (1) (1) (1) (1) (1) fd fd fd fd fd 3 3 3 3 3 fd fd fd fd fd 2 2 2 2 2 (2) (2) (2) (2) (2) ry/by1 ry/by1 ry/by1 ry/by1 ry/by1 embedded program algorithm fd 7 toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspended program fd 7 toggle 0 n/a n/a 0 standard standard standard standard standard mode mode mode mode mode erase erase erase erase erase suspend suspend suspend suspend suspend mode mode mode mode mode parameter parameter parameter parameter parameter symbol symbol symbol symbol symbol -100 -100 -100 -100 -100 -120 -120 -120 -120 -120 -150 -150 -150 -150 -150 unit unit unit unit unit min min min min min max max max max max min min min min min max max max max max min min min min min max max max max max write cycle time t avav t wc 100 120 150 ns write enable setup time t wlel t ws 000 ns chip select pulse width t eleh t cp 45 50 50 ns address setup time t avel t as 000 ns data setup time t dveh t ds 45 50 50 ns data hold time t ehdx t dh 000 ns address hold time t elax t ah 45 50 50 ns chip select pulse width high t ehel t cph 20 20 20 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase time t whwh2 15 15 15 sec read recovery time (2) t ghel 000 s chip programming time 50 50 50 sec after writing a sector erase command sequence, the system may read fd3 to determine whether or not an erase opera- tion has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each addi- tional sector erase command. when the time-out is com- pleted, fd3 switches from ?0? to ?1.? the system may ignore fd3 if the system can guarantee that the time between addi- tional sector erase commands will always be less than 50s. see also the ?sector command sequence? section. after the sector erase command sequence is written, the f lash ac c haracteristics ? w rite /e rase /p rogram o perations ,cs c ontrolled (vcc = 3.3v, vss = 0v, ta = -55c to +125c) 1. typical value for twhwh1 is 9s. 2. guaranteed by design, but not tested. fd3: sector erase timer system should read the status on fd7/fd23 (data polling) or fd6/fd22 (toggle bit i) to ensure the device has accepted the command sequence, and then read fd3/fd19. if fd3/ fd19 is high (?1?) the internally controlled erase cycle has begun; all further commands (other than erase suspend) will be ignored until the erase operation is completed. if fd3/fd19 is low (?0?). the device will accept additional sec- tor erase commands. to ensure the command has been accepted, the system software should check the status of fd3/fd19 prior to and following each subsequent sector erase command. if fd3/fd19 is high on the second status check, the last command may not have been accepted. table 8 shows the inputs for fd3/fd19.
30 30 30 30 30 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx f lash ac c haracteristics ? w rite /e rase /p rogram o perations - we c ontrolled (vcc = 3.3v, ta = -55c to +125c) parameter parameter parameter parameter parameter symbol symbol symbol symbol symbol -100 -100 -100 -100 -100 -120 -120 -120 -120 -120 -150 -150 -150 -150 -150 unit unit unit unit unit min min min min min max max max max max min min min min min max max max max max min min min min min max max max max max write cycle time t avav t wc 100 120 150 ns chip select setup time t elwl t cs 000 ns write enable pulse width t wlwh t wp 50 50 65 ns address setup time t avwl t as 000 ns data setup time t dvwh t ds 50 50 65 ns data hold time t whdx t dh 000 ns address hold time t wlax t ah 50 50 65 ns write enable pulse width high t whwl t wph 30 30 35 ns duration of byte programming operation (1) t whwh1 300 300 300 s sector erase t whwh2 15 15 15 sec read recovery time before write (3) t gh w l 000 s v cc setup time t vcs 50 50 50 s chip programming time 50 50 50 sec output enable setup time t oes 000 ns output enable hold time (2) t oeh 10 10 10 ns 1. typical value for twhwh1 is 9s. 2. for toggle and data polling. 3. guaranteed by design, but not tested. f lash ac c haracteristics ? r ead -o nly o perations (vcc = 3.3v, ta = -55c to +125c) parameter parameter parameter parameter parameter symbol symbol symbol symbol symbol -100 -100 -100 -100 -100 -120 -120 -120 -120 -120 -150 -150 -150 -150 -150 unit unit unit unit unit min min min min min max max max max max min min min min min max max max max max min min min min min max max max max max read cycle time t avav t rc 100 120 150 ns address access time t avqv t acc 100 120 150 ns chip select access time t elqv t ce 100 120 150 ns output enable to output valid t glqv t oe 40 50 55 ns chip select high to output high z (1) t ehqz t df 30 30 40 ns output enable high to output high z (1) t ghqz t df 30 30 40 ns output hold from addresses, fcs or foe change, t axqx t oh 000ns whichever is first 1. guaranteed by design, not tested. ac t est c ircuit ac t est c onditions notes: vz is programmable from -2v to +7v. iol & ioh programmable from 0 to 16ma. tester impedance z0 = 75 ? . vz is typically the midpoint of voh and vol. iol & ioh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. parameter parameter parameter parameter parameter typ typ typ typ typ unit unit unit unit unit input pulse levels v il = 0, v ih = 2.5 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v fig. 10
31 31 31 31 31 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx f lash ac w aveforms f or r ead o pera tions fig. 11
32 32 32 32 32 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx notes: notes: notes: notes: notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. fd7 is the output of the complement of the data written to each chip. 4. fdout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. f lash w rite /e rase /p rogram o pera tion , fwe c ontrolled fig. 12
33 33 33 33 33 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx f lash ac w aveforms c hip /s ector e rase o pera tions note: note: note: note: note: 1. sa is the sector address for sector erase. fig. 13
34 34 34 34 34 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx f lash ac w aveforms for d ata p olling d uring e mbedded a lgorithm o pera tions fig. 14
35 35 35 35 35 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx notes: 1. fpa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. fd7 is the output of the complement of the data written to each chip. 4. fdout is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. f lash a lternate f cs c ontrolled p rogramming o peration t imings fig. 15
36 36 36 36 36 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx t emporary s ector u nprotect o peration 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. parameter parameter parameter parameter parameter description description description description description all speed options all speed options all speed options all speed options all speed options unit unit unit unit unit t vidr vid rise and fall time (see note) min 500 ns t rsp rst setup time for temporary sector min 4 s unprotect t emporary s ector u nprotect t iming d iagram fig. 16 fig. 17
37 37 37 37 37 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx ac c haracteristics s ector p rotect /u nprotect t imiing d iagram fig. 18
38 38 38 38 38 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx h ardware r eset (rst) parameter parameter parameter parameter parameter description description description description description test setup test setup test setup test setup test setup all speed options all speed options all speed options all speed options all speed options unit unit unit unit unit t ready rst pin low (during embedded algorithms) to read or write (see note) max 20 s t ready rst pin low ( not during embedded algorithms) to read or write (see note) max 500 ns t rp rst pulse width min 500 ns t rh rst high time before read (see note) min 50 ns t rpd rst low to standby mode min 20 s t rb ry/by1 recovery time min 0 ns note: not 100% tested. fig. 19
39 39 39 39 39 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx ac c haracteristics dq2 vs . dq 6 fig. 20
40 40 40 40 40 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx t oggle b it t imings (d uring e mbedded a lgorithms ) fig. 21
41 41 41 41 41 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx 275 p lastic b all g rid a rray (pbga) all linear dimensions are millimeters and parenthetically in inches b ottom v iew package 743:
42 42 42 42 42 white electronic designs corporation phoenix az (602) 437-1520 white electronic designs wedpnf8m722v-xbx 750 powerpc? system block diagram
43 43 43 43 43 white electronic designs corporation (602) 437-1520 www.whiteedc.com white electronic designs wedpnf8m722v-xbx device grade: device grade: device grade: device grade: device grade: m = military -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package: package: package: package: package: b = 275 plastic ball grid array (pbga) frequency (mhz) frequency (mhz) frequency (mhz) frequency (mhz) frequency (mhz) 1010 = 100mhz sdram / 100ns flash 1012 = 100mhz sdram / 120ns flash 1015 = 100mhz sdram / 150ns flash 1210 = 125mhz sdram / 100ns flash 1212 = 125mhz sdram / 120ns flash 1215 = 125mhz sdram / 150ns flash 3.3v power supply 3.3v power supply 3.3v power supply 3.3v power supply 3.3v power supply flash configuration, 1m x 8/512k x 16 (1mb) flash configuration, 1m x 8/512k x 16 (1mb) flash configuration, 1m x 8/512k x 16 (1mb) flash configuration, 1m x 8/512k x 16 (1mb) flash configuration, 1m x 8/512k x 16 (1mb) sdram configuration, 8m x 72 (64mb) sdram configuration, 8m x 72 (64mb) sdram configuration, 8m x 72 (64mb) sdram configuration, 8m x 72 (64mb) sdram configuration, 8m x 72 (64mb) flash flash flash flash flash sdram sdram sdram sdram sdram plastic plastic plastic plastic plastic white electronic designs corp. white electronic designs corp. white electronic designs corp. white electronic designs corp. white electronic designs corp. wed wed wed wed wed p p p p p n n n n n f 8m f 8m f 8m f 8m f 8m 72 72 72 72 72 1 1 1 1 1 v - v - v - v - v - xxxx xxxx xxxx xxxx xxxx b b b b b x x x x x ordering information

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